View MH8S72BMG-8_1279079.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
DESCRIPTION
The MH8S72BMG is 8388608 - word by 72-bit Synchronous DRAM module. This consists of ten industry standard 4Mx16 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP. The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required. This is a socket type - memory modules, suitable for easy interchange or addition of modules.
85pin
1pin
94pin 95pin
10pin 11pin
FEATURES
Frequency -7 -8 -10 100MHz 100MHz 100MHz CLK Access Time
(Component SDRAM)
6.0ns(CL=3) 6.0ns(CL=3) 8.0ns(CL=3)
Back side
Front side
Utilizes industry standard 4M x 16 Synchronous DRAMs TSOP and industry standard EEPROM in TSSOP 168-pin (84-pin dual in-line package)
124pin 125pin
40pin 41pin
single 3.3V0.3V power supply Clock frequency 100MHz Fully synchronous operation referenced to clock rising edge 4 bank operation controlled by BA0,1(Bank Address) /CAS latency- 2/3(programmable) Burst length- 1/2/4/8/Full Page(programmable) Burst type- sequential / interleave(programmable) Column access - random Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycle /64ms LVTTL Interface Discrete IC and module design conform to PC100 specification. (module Spec. Rev. 1.0 and SPD 1.2A(-7,-8), SPD 1.0(-10))
168pin 84pin
APPLICATION
PC main memory
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 1 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
PIN NO. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 PIN NAME VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD /CAS DQMB4 DQMB5 /S1 /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 NC PIN NO. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 PIN NAME VSS CKE0 /S3 DQMB6 DQMB7 NC VDD NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
PIN NAME VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD /WE0 DQMB0 DQMB1 /S0 NC VSS A0 A2 A4 A6 A8 A10 BA1 VDD VDD CK0
PIN NO. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
PIN NAME VSS NC /S2 DQMB2 DQMB3 NC VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VDD
NC = No Connection
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 2 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM /S2 /S3
Block Diagram /S0 DQMB0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
/S1 DQMB2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
10
D0
D5
D3
D8
DQMB4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQMB6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQMB1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQMB3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
D1
D6
D4
D9
DQMB5
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQMB7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
D2
D7 D7
CK0 CK1 CK2 CK3 /RAS /CAS /WE BA0,BA1,A<11:0> Vcc Vss
10
3SDRAMs+10pF 3SDRAMs+10pF 2SDRAMs+15pF 2SDRAMs+15pF D0 - D9 D0 - D9 D0 - D9 D0 - D9 D0 - D9 D0 - D9 CKE1 CKE0 SERIAL PD SCL WP 47K A0 A1 A2 SA0 SA1 SA2 SDA 3.3V 10K D5-D9 D0-D4
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 3 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
PIN FUNCTION
CK (CK0 ~ CK3) Input Master Clock:All other inputs are referenced to the rising edge of CK Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input.Self refresh is maintained as long as CKE is low. Chip Select: When /S is high,any command means No Operation. Combination of /RAS,/CAS,/WE defines basic commands. A0-11 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-11.The Column Address is specified by A0-7.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. Bank Address:BA0,1 is not simply BA.BA specifies the bank to which a command is applied.BA0,1 must be set with ACT,PRE,READ,WRITE commands
CKE0
Input
/S (/S0-3) /RAS,/CAS,/WE
Input Input
A0-11
Input
BA0,1 DQ0-63, CB0-7
Input
Input/Output Data In and Data out are referenced to the rising edge of CK Input Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.
DQMB0-7
Vdd,Vss SCL SDA SA0-3
Power Supply Power Supply for the memory mounted module. Input Output Input Serial clock for serial PD Serial data for serial PD Address input for serial PD
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 4 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH8S72BMG provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.
CK /S /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H] ACT command activates a row in an idle bank indicated by BA. Read(READ) [/RAS =H,/CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA). Write(WRITE) [/RAS =H, /CAS = /WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS =L, /CAS =H,/WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 5 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Adress Entry & Bank Activate Single Bank Precharge Precharge All Bank Column Address Entry & Write Column Address Entry & Write with AutoPrecharge Column Address Entry & Read Column Address Entry & Read with Auto Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE CKE CKE n-1 n H H H H H H X X X X X X /S H L L L L L /RAS /CAS X H L L L H X H H H H L /WE BA0,1 X H H L L L X X V V X V A11 X X V X X X A10 X X V L H L A0-9 X X V X X V
WRITEA
H
X
L
H
L
L
V
X
H
V
READ
H
X
L
H
L
H
V
X
L
V
READA REFA REFS REFSX TERM MRS
H H H L L H H
X H L H H X X
L L L H L L L
H L L X H H L
L L L X H H L
H H H X H L L
V X X X X X L
X X X X X X L
H X X X X X L
V X X X X X V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number NOTE: 1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 6 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Current State IDLE /S H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L /RAS /CAS X H H H L L L L X H H H H L L L L X H H H X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 Address Command DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST NOP NOP ILLEGAL*2 Bank Active,Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read,Latch CA, Determine Auto-Precharge Begin Write,Latch CA, Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst Terminate Burst,Latch CA, READ/READA Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, L L L L L H L L L L L H H L L L H L H L BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 ACT PRE/PREA REFA MRS Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL Action
READ/WRITE ILLEGAL*2
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 7 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State WRITE /S H L L L /RAS /CAS X X H H H H H L /WE Address X X HX L BA H BA,CA,A10 Action DESEL NOP(Continue Burst to END) NOP NOP(Continue Burst to END) TBST Terminate Burst Terminate Burst,Latch CA, READ/READA Begin Read,Determine AutoPrecharge*3 Terminate Burst,Latch CA, WRITE/ Begin Write,Determine AutoWRITEA Precharge*3 ACT Bank Active/ILLEGAL*2 PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL Command
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 8 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State PRE CHARGING /S H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS /CAS X H H H L L L L X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST ACT PRE/PREA REFA MRS Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) ILLEGAL ILLEGAL NOP(Row Active after tRCD NOP(Row Active after tRCD ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 9 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING /S H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS /CAS X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X BA BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL
READ/WRITE ILLEGAL ACT PRE/PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL
READ/WRITE ILLEGAL ACT PRE/PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state.May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 10 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
Current State SELF REFRESH*1 CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CKE n X H H H H H L X H L H L L L L L L X H L H L /S X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP(Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function Truth Table Begin CK0 Suspend at Next Cycle*3 Exit CK0 Suspend at Next Cycle*3 Maintain CK0 Suspend Action
ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care NOTES: 1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All banks idle State. 3. Must be legal command.
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 11 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX MRS
MODE REGISTER SET
REFA
IDLE
AUTO REFRESH
CKEL
CLK SUSPEND
CKEL CKEH TBST(for Full Page)
CKEH ACT
POWER DOWN
TBST(for Full Page)
ROW ACTIVE
WRITE WRITEA READA READ WRITE READ
CKEL
CKEL
WRITE SUSPEND
WRITE
CKEH
READ
CKEH
READ SUSPEND
WRITEA WRITEA CKEL READA
READA
CKEL
WRITEA SUSPEND
WRITEA
CKEH PRE
PRE PRE
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER ON
PRE
PRE CHARGE Automatic Sequence Command Sequence
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 12 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500us. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CK /S BA0 BA1 A11 A10 A9 0 0 0 0 WM A8 0 A7 A6 0 A5 A4 A3 BT A2 A1 A0 BL /RAS /CAS LTMODE /WE BA0,1 A11-0 BL 000 001 010 011 100 101 110 111 0 1 BT= 0 1 2 4 8 R R R FP SEQUENTIAL INTERLEAVED
V
BT= 1 1 2 4 8 R R R R
LATENCY MODE
CL 000 001 010 011 100 101 110 111 0 1
/CAS LATENCY R R 2 3 R R R R BURST SINGLE BIT
BURST LENGTH
BURST TYPE
WRITE MODE
R:Reserved for Future Use FP: Full Page
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 13 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
[ /CAS LATENCY] /CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the speed of CLK determines which CL should be used.First output data is available after CL cycles from READ command.
/CAS Latency Timing(BL=4)
CK Command
ACT tRCD READ
Address
X
Y CL=2
DQ DQ
Q0
Q1
Q2
Q3
CL=2 Q3
CL=3
Q0
Q1
Q2
CL=3
[ BURST LENGTH ] The burst length,BL,determines the number of consecutive wrutes or reads that will be automatically performed after the initial write or read command.For BL=1,2,4,8,full page the output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2) tRCD
CK Command
ACT
READ
Address DQ DQ DQ DQ DQ
X
Y
Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q2 Q1 Q2 Q1 Q2 Q3 Q3 Q4 Q5 Q6 Q3 Q4 Q5 Q6 Q7 Q7 Q8 Qm Q0 Q1
BL=1 BL=2 BL=4 BL=8 BL=FP
m=255
Full Page counter rolls over and continues to count. 29. Oct.1998
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 14 / 55 )
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
CK Command Address DQ CL= 3 BL= 4 /CAS Latency
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
Burst Length Burst Type
Burst Length
Initial Address BL A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 2 1 1 0 2 3 0 3 0 1 0 1 1 2 4 5 6 7 0 1 5 6 7 0 1 2 6 7 0 1 2 3 7 0 1 2 3 0 0 1 2 3 1 2 3 4 0 1 2 3 1 2 3 4 2 3 4 5 Sequential 3 4 5 6 4 5 6 7 5 6 7 0
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 15 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum activation interval between one bank and the other bank is tRRD.The number of banks which are active concurrently is not limited. PRECHARGE The PRE command deactivates indicated by BA. When both banks are active, the precharge all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command can be issued. Bank Activation and Precharge All (BL=4, CL=3)
CLK
2ACT command/tRCmin tRCmin PRE tRAS Xb tRCD Xb Xb 01 00 Qa0 Qa1 Qa2 Qa3 Y 0 1 tRP Xb Xb Xb 01 ACT
Command A0-9 A10 A11 BA0,1 DQ
ACT tRRD Xa Xa Xa 00
ACT READ
READ After tRCD from the bank activation, a READ command can be issued. 1st output date is available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when the Burst Length is BL. The start address is specified by A7-0, and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8) by interleaving the dual banks. When A10 is high at a READ command, the auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge start at BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA.
Precharge all
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 16 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Multi Bank Interleaving READ (BL=4, CL=3)
CK Command A0-9 A10 A11 BA0,1 DQ
/CAS latency
ACT tRCD Xa Xa Xa 00
READ ACT Y 0 Xb Xb Xb 00 10 Qa0
READ PRE Y 0 0
10 Qa1
00 Qa2 Qa3 Qb0 Qb1 Qb2
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CK
BL + tRP
Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa 00
READ BL Y 1 tRP
ACT Xa Xa Xa
00 Qa0 Qa1 Qa2 Qa3
00
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
CK Command CL=3 CL=2 DQ DQ
Qa0 ACT READ BL Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Qa3
Internal Precharge Start Timing
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 17 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A7-0, and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time(tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing. The Mode Register can be WRITE command is issued and the remaining burst length is ignored.The read data burst length os unaffected while in this mode.
Multi Bank Interleaving WRITE (BL=4)
CK Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa 00 00 Da0 Y 0 Xb Xb Xb 10 Da1 Da2 Da3 10 Db0 Write ACT tRCD Y 0 0 0 00 Db1 Db2 Db3 0 0 10 Write PRE PRE
WRITE with Auto-Precharge (BL=4)
CK Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa 00 00 Da0 Da1 Da2 Da3 Y 1 Write tWR tRP Xa Xa Xa 00 ACT
Internal precharge begins
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 18 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
[ BURST WRITE ] A burst write operation is enabled by setting A9=0 at MRS.A burst write stats in the same cycle as a write command set.(The latency of data input is 0.) The burst length can be set to 1,2,4,8,and full-page,like burst read operations.
tRCD
CK Command
ACT
READ
Address DQ DQ DQ DQ DQ
X
Y
Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q2 Q1 Q2 Q1 Q2 Q3 Q3 Q4 Q5 Q6 Q3 Q4 Q5 Q6 Q7 Q7 Q8 Qm Q0 Q1
BL=1 BL=2 BL=4 BL=8 BL=FP
m=255
Full Page counter rolls over and continues to count.
[ SINGLE WRITE ] A single write operation is enabled by setting A9=1 at MRS.In a single write operation,data is written only to the column address specified by the write command set cycle without regard to the burst length setting.(The latency of data input is 0.)
CK Command
ACT
READ
tRCD
Address DQ
X
Y
Q0
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 19 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
BURST INTERRUPTION [ Read Interrupted by Read ] Burst read option can be interrupted by new read of any bank. Random column access is allowed. READ to READ interval is minimum 1 CK Read Interrupted by Read (BL=4, CL=3)
CK Command A0-9 A10 A11 BA0,1 DQ
00 00 10 Qai0 Qaj0 01 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3 READ READ Yi 0 Yj 0 READ Yk 0 READ Yl 0
[ Read Interrupted by Write ] Burst read operation can be interrupted by write of the same or the other bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion. Read Interrupted by Write (BL=4, CL=3)
CK Command A0-9 A10 A11 BA0,1
0 0 READ Yi 0 Write Yj 0
DQMB0-7 Q D
Qai0 Daj0 Daj1 Daj2 Daj3
DQM control Write control
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 20 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same or the other bank. Read to PRE interval is minimum 1 CK. A PRE command output disable latency is equivalent to the /CAS Latency.As a result, READ to PRE interval determines valid data length to be output.The figure below shows examples of BL=4. Read Interrupted by Precharge (BL=4)
CK
Command DQ
READ
PRE Q0 Q1 Q2
CL=3
Command DQ Command DQ
READ PRE Q0 READ PRE Q0 Q1
Command DQ
READ Q0
PRE Q1 Q2
CL=2
Command DQ Command DQ
READ PRE Q0 READ PRE Q0 Q1
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 21 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ] Similarly to the precharge, burst terminate command,TBST, can interrupt burst read operation and disable the data output. READ to TBST interval is minimum of 1 CK. TBST is mainly used to interrupt FP bursts.The figure below show examples, of how the output data is terminated with TBST.
Read Interrupted by Burst Terminate (BL=4)
CK
Command DQ Command
READ Q0
TBST Q1 Q2 Q3
READ
TBST Q0 Q1 Q2
CL=3
DQ Command DQ
READ TBST Q0
Command DQ Command
READ Q0 Q1
TBST Q2 Q3
READ Q0
TBST Q1 Q2
CL=2
DQ
Command DQ
READ TBST Q0
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 22 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
[ Write Interrupted by Write ] Burst write operation can be interrupted by new write of the same or the other bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CK. Write Interrupted by Write (BL=4)
CK Command A0-9 A10 A11 BA0,1 DQ
00 Dai0 00 Daj0 Daj1 10 00 Dal1 Dal2 Dal3 Write Write Yi 0 Yj 0 Write Yk 0 Write Yl 0
Dbk0 Dbk1 Dbk2 Dal0
[ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ at the interrupting READ cycle is "don't care". Write Interrupted by Read (BL=4, CL=3)
CK Command A0-9,11 A10 A11 BA0,1 DQMB0-7 DQ
Dai0 Qaj0 Qaj1 Dbk0 Dbk1 Qbl0 00 00 10 00 Write READ Yi 0 Yj 0 Write Yk 0 READ Yl 0
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 23 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed. Because the write recovery time(tWR) is required from the last data to PRE command. Write Interrupted by Precharge (BL=4)
CK Command A0-9,11 A10 A11 BA0,1 DQMB0-7 DQ
Dai0 Dai1 Dai2 00 00 Write tWR Yi 0 0 PRE tRP Xb Xb Xb 00 ACT
[ Write Interrupted by Burst Terminate ] A burst terminate command TBST can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active (Please see the waveforms below).The WRITE to TBST minimum interval is 1CK.
Write Interrupted by Burst Terminate (BL=4)
CK Command A0-9 A10 BA0,1 DQMB0-7 DQ
Dai0 Dai1 Dai2 Write Yi 0 0 TBST
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 24 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L, /WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on 4bank concurrentry. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to Auto-refresh interval is minimum tRC.Any command must not be supplied to the device before tRC from the REFA command.
Auto-Refresh
CK /S NOP or DESLECT /RAS /CAS /WE CKE A0-11 BA0,1
minimum tRC
Auto Refresh on All Banks
Auto Refresh on All Banks
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 25 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L, /WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is kept low.During the self-refresh mode, CKE is asynchronous and the only enabled input , all other inputs including CK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CK inputs, asserting DESEL or NOP command and then asserting CKE(REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle state and a new command can be issued after tRC, but DESEL or NOP commands must be asserted till then. Self-Refresh
CK
Stable CK
/S /RAS /CAS /WE CKE
NOP
tSRX A0-11 BA0,1
new command X 00
Self Refresh Entry
Self Refresh Exit
minimum tRC +1 CLOCK for recovery
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 26 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle, A command at the following cycle is ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CK CKE Command
PRE Standby Power Down
NOP NOP NOP NOP NOP NOP NOP
CKE Command
ACT
Active Power Down
NOP NOP NOP NOP NOP NOP NOP
DQ Suspend by CKE
CK CKE Command
Write READ
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 27 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
DQM CONTROL DQMB0-7 is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7 to write mask latency is 0. During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z latency is 2. DQM Function
CK Command DQMB0-7
Write READ
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQM=H
disabled by DQM=H
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 28 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VI VO IO Pd Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta=25C Condition with respect to Vss with respect to Vss with respect to Vss Ratings -0.5 ~ 4.6 -0.5 ~ Vdd+0.5 -0.5 ~ Vdd+0.5 50 10 0 ~ 70 -40 ~ 100 Unit V V V mA W C C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70C, unless otherwise noted) Symbol Vdd Vss VIH VIL Parameter Min. Supply Voltage Supply Voltage High-Level Input Voltage all inputs Low-Level Input Voltage all inputs 3.0 0 2.0 -0.3 Limits Typ. 3.3 0 Max. 3.6 0 Vdd+0.3 0.8 Unit V V V V
Note:* VIH (max) = Vdd+2.0V AC for pulse width<=3ns acceptable. VIL (min) = -2V AC for pulse width< =3ns acceptable.
CAPACITANCE
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted) Symbol CI(A) CI(C) CI(K) CI(S) CI(E) Parameter Input Capacitance, address pin
Input Capacitance, /RAS,/CAS,/WE
Test Condition
Limits(max.) 65 65
Unit pF pF pF pF pF pF pF
Input Capacitance, CK pin Input Capacitance, /CS pin Input Capacitance, CKE pin
VI = Vss f=1MHz Vi=25mVrms
45 40 65 40 22
CI(M) Input Capacitance, DQM pin CI/O Input Capacitance, I/O pin MITSUBISHI ELECTRIC ( 29 / 55 )
MIT-DS-0222-0.5
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted)
Limits (max) -7, -8
operating current one bank active (discrete)
Parameter
Symbol Icc1 Icc2P
Test Condition tRC=min.tCLK=min, BL=1, IOL=min
Unit -10 560 20 10 220 200 20 10 mA mA mA mA mA mA mA mA mA mA mA mA
685 20 10 220 200 20 10
precharge stanby current in power-down mode precharge stanby current in non power-down mode active stanby current in power-down mode active stanby current in non power-down mode
one bank active (discrete)
CKE=VILmax,tCLK=15ns Icc2PS CKE=CLK=VILmax(fixed) Icc2N CKE=/CS=VIHmin,tCLK=15ns(Note) Icc2NS CKE=VIHmin,CLK=VILmax(fixed) Icc3P CKE=VILmax,tCLK=15ns Icc3PS CKE=CLK=VILmax(fixed)
burst current auto-refresh current self-refresh current
550 Icc3N CKE=/CS=VIHmin,tCLK=15ns 400 Icc3NS CKE=VIHmin,CLK=VILmax(fixed) 735 Icc4 tCLK=min, BL=4, CL=3,IOL=0mAall banks active(discerte) tRC=min, tCLK=min 1500 Icc5 Icc6 CKE <0.2V 10
450 400 735 1150 10
Note:Input signals are changed one time during 30ns. Note:All other pins not under test are 0V.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted)
Symbol VOH(DC) VOL(DC) VOH(AC IOZ ) VOL(AC) Ii Parameter High-Level Output Voltage(DC) Low-Level Output Voltage(DC) Off-stare Output Current High-Level Output Voltage(AC) Input Current Low-Level Output Voltage(AC) Test Condition IOH=-2mA IOL=2mA Q floating CL=50pF, VO=0 ~ Vdd IOH=-2mAIOL=2mA VIH=0 ~ Vdd+0.3V CL=50pF, Limits Unit Min. Max. 2.4 V 0.4 V -10 2 10 uA V 0.8 V -50 50 uA
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 30 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V Symbol Parameter tCLK CL=2 -7 Min. Max. 10 10 3 3 1 10 2 1 70 20 50 100K 20 10 20 10 20 10 64 Limits -8 Min. Max. 13 10 3 3 1 10 2 1 70 20 50 100K 20 10 20 10 20 10 64 -10 Unit Min. Max. 15 10 4 4 1 3 1 90 30 60 30 10 20 10 20 10 ns ns ns ns 10 ns ns ns ns ns 100K ns ns ns ns ns ns ns 64 ms
Note
CL=3 tCH CK High pulse width tCL CK Low pilse width tT Transition time of CK tIS Input Setup time(all inputs) tIH Input Hold time(all inputs) tRC Row cycle time tRCD Row to Column Delay tRAS Row Active time tRP Row Precharge time tWR Write Recovery time tRRD Act to Act Deley time tCCD Col to Col Delay time tRSC Mode Register Set Cycle time tSRX Self Refresh Exit time tREF Refresh Interval time
CK cycle time
1 1 1 1
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns should be added to the parameter.
1.4V
CK
Any AC timing is referenced to the input
Signal
1.4V
signal crossing through 1.4V.
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 31 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise note3) Symbol Parameter tAC Access time from CK CL=2 CL=3 tOH tOLZ tOHZ Output Hold time from CK Delay time, output low impedance from CK Delay time, output high impedance from CK 3 0 3 6 Limits -7 -8 -10 Unit Min. Max. Min. Max. Min. Max. 6 6 3 0 3 6 7 6 3 0 3 8 8 8 ns ns ns ns ns
Note:3 If tr(clock rising time) is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
50
VTT=1.4V
CK
1.4V
VREF=1.4V VOUT 50pF
DQ
1.4V
Output Timing Measurement Reference Point
CK
1.4V
DQ
tAC tOH
tOHZ
1.4V
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 32 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Burst Write (single bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE
tWR
CKE DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0
X Y X Y
X
X
X
X
0
0
0
0
0
D0
D0
D0
D0
D0
D0
D0
D0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 33 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Burst Write (multi bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
tRAS
tRP tRCD
/RAS
tRCD
/CAS /WE
tWR tWR
CKE DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0
X X Y Y X X Y
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 34 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Burst Read (single bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE CKE DQM
DQM read latency =2
A0-8 A10 A9,11 BA0,1 DQ
X
Y
X
Y
X
X
X
X
0
0
0
0
0
CL=3
Q0 Q0 Q0 Q0 Q0 Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
READ to PRE BL allows full data out
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 35 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Burst Read (multiple bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRAS tRP tRCD tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency =2
A0-8 A10 A9,11 BA0,1 DQ
X
X
Y
Y
X
X
Y
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
0
CL=3
Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1 Q0
ACT#0
READ#0 ACT#1
PRE#0 READ#1
ACT#0 PRE#1
READ#0 ACT#2
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 36 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD BL-1+ tWR + tRP BL-1+ tWR + tRP tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0 ACT#1
X X Y Y X Y X Y
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
1
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
D1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 37 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD BL+tRP BL+tRP tRCD
/CAS /WE CKE DQM
DQM read latency =2
A0-8 A10 A9,11 BA0,1 DQ
X
X
Y
Y
X
Y
X
Y
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
1
CL=3
Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1
CL=3
Q0 Q0
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 38 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Page Mode Burst Write (multi bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0
X X Y Y Y Y
X
X
X
X
0
1
0
0
1
0
D0
D0
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 39 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency=2
A0-8 A10 A9,11 BA0,1 DQ
X
X
Y
Y
Y
Y
X
X
X
X
0
1
0
0
1
0
CL=3
Q0 Q0
CL=3
Q0 Q0 Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1
ACT#0
READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 40 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Write Interrupted by Write / Read @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD tCCD
/CAS /WE CKE
DQM A0-8 A10 A9,11 BA0,1 DQ
X X Y Y Y Y Y
X
X
X
X
0
1
0
0
0
1
0
CL=3
D0 D0 D0 D0 D0 D0 D1 D1 Q0 Q0 Q0 Q0
ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 41 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Read Interrupted by Read / Write @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency=2
A0-8 A10 A9,11 BA0,1 DQ
X
X
Y
Y
Y
Y
Y
Y
X
X
X
X
0
1
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 42 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Write Interrupted by Precharge @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X X Y Y X Y
X
X
X
X
X
X
0
1
0
1
0
1
1
1
D0
D0
D0
D0
D1
D1
D1
D1
D1
ACT#0 WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted by Precharge of the other bank.
Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 43 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Read Interrupted by Precharge @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD tRP
/RAS
tRCD tRCD
/CAS /WE CKE DQM
DQM read latency=2
A0-8 A10 A9,11 BA0,1 DQ
X
X
Y
Y
X
Y
X
X
X
X
X
X
0
1
0
1
0
1
1
1
Q0
Q0
Q0
Q0
Q1
Q1
ACT#0
READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read is not interrupted by Precharge of the other bank.
Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 44 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Mode Register Setting
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRC
tRSC
/RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
Auto-Ref (last of 8 cycles) Mode Register Setting ACT#0
0 M X Y
X
X
0
0
D0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 45 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Auto-Refresh @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRC
/RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
Auto-Refresh Before Auto-Refresh, all banks must be idle state. ACT#0
X Y
X
X
0
0
D0
D0
D0
D0
WRITE#0
After tRC from Auto-Refresh, all banks are idle state. Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 46 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Self-Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
CLK can be stopped tRC
/CS /RAS /CAS /WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM A0-8 A10 A9,11 BA0,1 DQ
Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state. Self-Refresh Exit After tRC from Self-Refresh Exit, all banks are idle state. Italic parameter indicates minimum case ACT#0
X
X
X
0
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 47 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
DQM Write Mask @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0
X Y Y Y
X
X
0
0
0
0
masked
D0 D0 D0 D0 D0 D0 D0
masked
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 48 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
DQM Read Mask @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE
DQM read latency=2
DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0 READ#0
X Y Y Y
X
X
0
0
0
0
masked
Q0 Q0 Q0 Q0
masked
Q0 Q0 Q0
READ#0
READ#0
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 49 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS /CAS /WE
Standby Power Down
CKE
CKE latency=1
Active Power Down
DQM A0-8 A10 A9,11 BA0,1 DQ
Precharge All ACT#0
X
X
X
0
Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 50 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
CLK Suspend @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE
CKE latency=1 CKE latency=1
DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0
X Y Y
X
X
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
WRITE#0 READ#0 CLK suspended
CLK suspended Italic parameter indicates minimum case
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 51 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Function described Defines # bytes written into serial memory at module mfgr Total # bytes of SPD memory device Fundamental memory type # Row Addresses on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly... ... Data Width continuation Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL). -7,-8,-10 -7,-8 -10
SPD enrty data 128 256 Bytes SDRAM A0-A11 A0-A7 2BANK x72 0 LVTTL 10ns 6ns 8ns
ECC
SPD DATA(hex) 80 08 04 0C 08 02 48 00 01 A0 60 80 02 80 10 10 01 8F 04 06 01 01 00 0E A0 D0 F0 60 70 80 00 00 14 1E 14 14 1E 32 3C
Cycle time for CL=3 SDRAM Access from Clock tAC for CL=3 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type SDRAM width,Primary DRAM Error Checking SDRAM data width
Minimum Clock Delay,Back to Back Random Column Addresses
self refresh(15.625uS) x16 x16 1 1/2/4/8/Full page 4bank 2/3 0 0
non-buffered,non-registered
Precharge All,Auto precharge Write1/Read Burst
Burst Lengths Supported # Banks on Each SDRAM device CAS# Latency CS# Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes:General SDRAM Cycle time(2nd highest CAS latency) Cycle time for CL=2
-7 -8 -10
10ns 13ns 15ns 6ns 7ns 8ns N/A N/A 20ns 30ns 20ns 20ns 30ns 50ns 60ns
24
SDRAM Access form Clock(2nd highest CAS latency)
-7 -8 -10
tAC for CL=2 25 26 27 28 29 30 SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum Row Active to Row Active Min. RAS to CAS Delay Min Active to Precharge Min
-7,-8 -10 -7,-8,-10 -7,-8 -10 -7,-8 -10
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 52 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Serial Presence Detect Table II
31 32 33 Density of each bank on module Command and Address signal input setup time Command and Address signal input hold time
-7,-8 -10 -7,-8 -10
32MByte 2ns N/A 1ns N/A 2ns N/A 1ns N/A option rev 1.2A rev 1 Check sum for -7 Check sum for -8 Check sum for -10
08 20 00 10 00 20 00 10 00 00 12 01 1F 5F 5C 1CFFFFFFFFFFFFFF 01 02 03 04
4D4838533732424D472D3720202020202020 4D4838533732424D472D3820202020202020 4D4838533732424C472D3130202020202020
34 35 36-61 62 63
Data signal input setup time Data signal input hold time Superset Information (may be used in future) SPD Revision Checksum for bytes 0-62
-7,-8 -10 -7,-8 -10
-7,-8 -10
64-71 72
Manufactures Jedec ID code per JEP-108E Manufacturing location
MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany
73-90
Manufactures Part Number
MH8S72BMG-7 MH8S72BMG-8 MH8S72BMG-10 PCB revision year/week code serial number option
-7,-8 -10
91-92 93-94 95-98 99-125 126 127
Revision Code Manufacturing date Assembly Serial Number Manufacture Specific Data Intetl specification frequency Intel specification CAS# Latency support
rrrr yyww ssssssss 00 64 66 FF FD 06 00
-7 -8 -10
100MHz 66MHz CL=2/3,AP,CK0-3 CL=3,AP,CK0-3 CL=2/3 open
128+
Unused storage locations
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 53 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
OUTLINE
4,45MAX
10.13
84
2-o30.1
R20.05
1.270.1 17.780.13 17.780.13 30.13 20.13 34.925
168
1.270.1 133.350.13 127.350.13 6.350.13 24.4950.13 9x1.27=11.430.2 29x1.27=36.830.2 42.180.13 6.350.1 43x1.27=54.610.2
85
1
30.13 10.13
8.890.13
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 54 / 55 )
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72BMG -7,-8, -10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party. 2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. 3.All information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. 4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. 5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 6.If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
MIT-DS-0222-0.5
MITSUBISHI ELECTRIC ( 55 / 55 )
29. Oct.1998

▲Up To Search▲

Price & Availability of MH8S72BMG-8

	To Download MH8S72BMG-8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .